Rising Applied sciences Are Driving System Stage Check Adoption

With the scale of semiconductor transistors lowering and chip complexity growing exponentially, semiconductor check has change into important to making sure that solely high-quality merchandise go to market. With the introduction of extra rigorous acceptable high quality degree (AQL) certifications, check strategies should always evolve to fulfill these requirements, and system degree check (SLT) and conventional check utilizing automated check tools (ATE) ship a complete check technique to make sure units exceed high quality necessities.

System degree check (SLT), which might determine and clear up quite a lot of check issues, just isn’t new expertise. It’s been used within the computing area because the late Nineties. Nonetheless, with the exponential progress of transistors built-in into the chip, the complexity of the chip is growing, and extra built-in chip (IC) producers are utilizing SLT to enhance the yield and high quality of their chips.

What Is System Stage Check and Why Is It Totally different?

System degree check, often known as practical check, is a technique of testing the system below check (DUT) in its finish use. By operating the working system and utilizing the system below check to carry out basic or focused software checks, further verification might be completed past that of conventional ATE testing. SLT checks are sometimes regular system operations with further verification steps.

Trade tendencies driving System Stage Check

Prior to now 20 years, the SLT market has grown significantly because of a number of tendencies within the chip business.

First, system high quality necessities are growing. Prior to now 10 years, individuals have change into extra depending on cellphones and different digital units, leading to more and more excessive necessities for the standard of chips. This has pushed producers to conduct complete checks for his or her chips and programs to cut back the potential for issues encountered by finish customers after buying merchandise. Due to this, SLT for cellular units has skilled speedy progress.

One other development is within the automotive area. In assisted autonomous automobiles, digital units and software program are used to sense and reply to occasions with automated steering or braking. Superior driver help programs (ADAS) require increased requirements, which implies that the efficiency of ultra-high-power and blended sign units, in addition to platform effectivity and thermal stability is important.

Chip suppliers proceed to drive expertise to the restrict to enhance efficiency, battery runtime and yield, which suggests they need to:

  • Ship merchandise from new course of nodes as early as doable, though the method fault price could also be excessive
  • Function at a voltage as little as doable to increase the battery runtime
  • Wonderful tune the phase-locked loop (PLL) setting to maximise yield
  • Undertake cutting-edge packaging expertise to enhance transistor density and efficiency

Moreover within the automotive infotainment sector, car firms are nearer to the forefront of expertise than ever earlier than. Adopting cutting-edge expertise to realize increased stability permits them to shorten the time to marketplace for automotive infotainment merchandise.

One other progress space for SLT is in huge information processing, and edge and cloud synthetic intelligence (AI) purposes, with their necessities for prime energy – from lots of to 1000’s of watts.

Given the number of necessities driving these numerous markets, it has change into important but in addition very advanced to make sure high-quality parts are shipped in completed merchandise. Because the expertise is continually pushed to its limits, using SLT has change into ever extra essential in stopping faults from being missed and making certain that parts attain the required high quality ranges. Along with enhancing product high quality, operating the tools as near the terminal software as doable assists in shortening the time to market.

Conventional Check Protection Turns into Extra Difficult

IC producers are always integrating extra features right into a single chip. Take cellular processors for example. Within the early days, performance was restricted primarily to telephone calls. Right this moment, cellular units assist graphics, picture processing, superior safety and extra. Prior to now, communications have been completed through digital processing however at the moment’s units embody voice and biometric information processing, and even AI algorithms. Due to this, the appliance processor (AP) must be built-in with the high-speed reminiscence.

Processors are evolving over time and the options they ship are increasing quickly. Options like monitoring well being metrics, recording and storage, connection and management, communications with peripheral automotive sensors to make sure security, and simplifying individuals’s lives by machine studying and AI are growing productiveness and security on a regular basis. Faults related to the interplay of those practical blocks could also be significantly tough to seize, particularly when the check interfaces inside them use totally different languages.

All of those new features are built-in into one AP, which suggests elevated transistor depend that in some instances outpaces Moore’s Legislation.

After all, check challenges transcend the system features. Once we combine a number of transistors into the IC, trade-offs should typically be made, resulting in the lack of check protection achieved through conventional strategies. With this enhance in transistor depend, the chance of faults is increased and extra checks are wanted to keep away from an elevated fault price. ATE check is not adequate to catch all faults and so SLT can be utilized to realize extra complete check protection.

Find out how to Run SLT?

SLT is a practical check of a product in a way carefully matching its finish use. The “system” half is carried out on a customized system degree check board and the check move contains:

  • Performing particular operations: operating the system’s basic features and goal purposes inherent within the system and verifying they work as anticipated. These operations can embody beginning chips, loading the working system, or operating particular applications written by a module, resembling efficiency analysis applications. The system degree check board used is just like the reference design or analysis board offered to the shopper.
  • Figuring out if the operation was profitable: measured in line with the check outcomes or the success/failure of the operation. For instance, when verifying whether or not an inner course of is efficiently executed, the working system is validated to verify it may be efficiently began or a selected worth is measured (e.g., a comparability between the efficiency check end result and the edge worth) as the premise for judgment.

Generally, the system in SLT is supplied with on-board processors to execute the check move. Since SLT primarily focuses on the system on a chip (SoC) and system in bundle (SiP) chips, the check processor is normally part of the system below check. If this isn’t the case, the peripheral check system of the system below check will have to be geared up with an appropriate processor.

The SLT board circuit across the system below check might change in line with the necessities. A fault escape report can rapidly and simply be displayed on display. Such a check is tough to realize on ATE as a result of a major quantity of fault evaluation should be carried out to hint the practical fault to the transistor degree. SLT is best suited to this sort of check as a result of it might probably use the precise use case that triggers the fault, and rapidly add this practical check to the SLT check, which might nearly instantly determine the basis reason behind the fault escape.

Nonetheless, since SLT is a practical check that simulates the actual terminal use situation, fairly than the structural checks we see in ATE, SLT check time is usually longer than that of conventional ATE. As such, parallel check effectivity turns into essential to sustaining the cost-effectiveness of SLT. ATE check time is usually primarily based on a unit of 10 seconds, whereas SLT check time relies on a unit of 1 to 10 minutes. To attain the very best effectivity, parallel testing should be an order of magnitude increased than ATE.

Value Issues

Within the ultimate evaluation, value issues. A complete check technique ensures faults are captured as early as doable, avoiding downstream course of prices. ATE wafer check performs effectively in capturing faults early within the course of, together with transistor degree issues, sensitivity to altering frequency/voltage ranges, and compliance with fundamental design specs.

Some faults are generated within the packaging course of, and ATE ultimate check is used to determine these points. Nonetheless, there are nonetheless some faults which can be so refined and sophisticated that the system won’t ever cross the check acceptance course of if a low faulty elements per million (DPPM) degree is required.

For typical high quality necessities, ATE prices sometimes enhance as check time will increase. This enhance is usually controllable and, to some extent, linear. Nonetheless, when a excessive complexity transistor out is required, the price of ATE will finally attain an inflection level within the curve and develop exponentially.

That is primarily as a result of it takes loads of time to determine these faults, and so they have to be examined with peripheral units. A few of these checks are accomplished on ATE at the moment, together with some parameter and practical checks. Nonetheless, in some instances, the variety of further circuits and the size of the check means this sort of check just isn’t viable on ATE. It’s fascinating to notice that the SLT value/check time doesn’t enhance with the rise in complexity as a result of it is just beginning or operating an software. Over the previous 50 years, ATE has been excellent at capturing transistor degree design parameter faults and can proceed to be essentially the most cost-effective method to take action. SLT needs to be used for checks that can not be carried out on ATE utilizing real-world chip software situations.

Why are the faults of many courses captured in ATE however not SLT? The reason being that, not like ATE, SLT doesn’t systematically check each transistor and its parameters, however solely checks a subset of real-world purposes within the system and delivers practical outcomes. It’s nearly inconceivable to run each conceivable software program to excite each transistor and generate faults.

The price-effectiveness of SLT is achieved through the use of it to discover a affordable share of faults which can be brought on by points that ATE can not check or by concurrently stimulating the chip and a number of IP modules round it. The price of check for every system could possibly be one quarter or much less in comparison with ATE as a result of concurrent testability (the variety of units examined at one time) being a lot increased.

With complexity persevering with to extend exponentially and the variety of mission important purposes persevering with to rise, combining ATE and SLT check is a perfect resolution for sustaining top quality ranges on the lowest value.

To some extent, ATE value is linearly associated to complexity/transistor depend and so it needs to be used to catch faults on the wafer and IC degree. SLT could be very cost-effective at screening out the previous few, tough to seek out faults on the finish of the check move. Subsequently, including SLT to the top of the prevailing ATE check move is usually essentially the most cost-effective technique for mission-critical purposes with very top quality necessities.

Why Teradyne?

Solely by using each ATE and SLT check can a complete check technique be achieved. By contemplating quite a lot of components, together with the required high quality degree and prices, firms can decide the very best steadiness between ATE and SLT.

One of many benefits of the Teradyne Titan™ SLT tester is true parallel check. Every chip is totally unbiased of its adjoining chips, which is a more practical solution to carry out SLT and batch processing.

As well as, Teradyne has a large-scale automated manufacturing platform that has been in use for greater than ten years. By combining our storage automation structure with our semiconductor check experience, Teradyne Titan delivers a complete SLT automation and check resolution.

SLT is a supplementary check step and an extension to ATE check to make sure the required high quality ranges are met. Teradyne supplies options that assist your complete check lifecycle, making certain our clients can obtain most check protection to ship the very best high quality merchandise to market whereas lowering check time and price.


SLT has existed for almost 30 years and is especially used for cutting-edge, large-scale digital computing purposes. Some faults can solely be seen in actual software situations and SLT is uniquely suited to this. It’s an application-level check of chips on system degree check boards utilizing devoted peripherals to seize the final 0.00xx% of faults and obtain the bottom doable error escape price.



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